1. Field of the Invention
The invention relates to a capacitive coupling chip-to-chip signal transmission system and particularly relates to a capacitive coupling chip-to-chip signal transmission system and a chip-to-chip capacitive coupling transmission circuit capable of self testing.
2. Description of Related Art
With the development of miniaturization and decreasing production costs of electronic products, IC chip miniaturization and three-dimensional stack packaging have become an important trend in the development of semiconductor technology. 3D die stacking is an emerging technology that reduces the wire length both within and across dies in a system. With 3D die stacking, dies of different types can be stacked with a high bandwidth, low latency, and low power interface. 3D (three-dimensional) IC stack technology will be an effective solution to the problems of serious delay and power consumption. 3D ICs promise “more than Moore” integration by packing a great deal of functionality into small form factors, while improving performance and reducing costs.
In the current technology for integrating 3D IC, the fabrication of vertical conduction between chips is a new technique for achieving chip interconnection. The methods for integrating the signal transmission between stack chips include wire bonding, micro-bumps, through silicon via (TSV), and contactless interconnect such as capacitive-coupling, and inductive-coupling. The 3D stack techniques not only achieve high I/O density but also satisfy the demand for high-speed transmission and low power consumption.
Among these techniques, the most common one is TSV technology. Major semiconductor manufacturers in the world are investing a lot in developing through silicon via (TSV) fabrication technology for 3D IC in an attempt to package various digital logics, memories, or analog chip circuit into one single package, so as to greatly improve system functionality and speed. Different from the conventional IC package bonding and salient point stacking technology, TSV technology achieves the greatest density of stacking chips in three-dimensional directions, has the smallest size, improves the speed of the devices, reduces signal delay, and suppresses power consumption. Therefore, TSV is the key technology for 3D IC integration. The more the stack layers are, the more powerful the functions of IC become.
However, TSV 3D IC faces technical problems related to wafer thinning, chip stack, and heat dissipation processing. In addition, as TSV 3D IC technology continues to advance and be applied to actual fabrication, more problems about details of the front-end and back-end IC fabrication processes are revealed. The major disadvantages thereof are high production costs and low yield rate. For example, the silicon substrates may be affected by the mechanical force of drilling, which lowers the yield rate of the chips.
In addition, for non-contact capacitive coupling or capacitive coupling chip communication, the main concept of AC coupled interconnect (ACCI) is that connection of DC electrical components is not required in case of high-frequency transmission, and the signal transmission can be completed simply by a good communication link. Capacitive coupling interconnection is a wireless chip-to-chip connection technology, and this technology utilizes capacitive coupling to transit signals from one chip to a neighboring chip. Moreover, the circuit design for a capacitive coupling chip transmission terminal is simpler and only requires sufficient driving and small coupling capacitive area. Thus, it is suitable for the integration of multiple chips. Capacitive coupling interconnection has advantages such as smaller area usage, higher I/O density, lower delay, lower power consumption of chip-to-chip I/O capability, and high performance, make it possible for forming a 3D package with high performance and economic efficiency.
However, for AC coupling interconnection, the circuit design of package is very important. The circuit and transmission method of AC coupling interconnection are related to the recovery accuracy of the transmitted signals. Thus, design issues such as I/O signal integrity needs to be overcome. On the other hand, for capacitive coupling interconnection technology, a testing method thereof cannot be achieved in the conventional 3D IC technology yet.